PGA technology provides the flexibility of on-site programming and re-programming without going through re-fabrication with a modified design. Partial Reconfiguration (PR) takes this flexibility one step further, allo wing the modification of an operating FPGA design by loading a partial configuration file, usually a partial BIT file. After a full BIT file configures the FPGA, partial BIT files can be downloaded to modify reconfigurable regions in the FPGA without compromising...
Project description: the Epiphany cores has limited amount of memory , a total of 32kb per core (512kb total) , however , it does have access to 1gb DDR , and SDCARD. in order to overcome the memory limitation , this project will implement a virtual memory interface on the Parallella , allowing for larger programs to run on it.