By: Intel Altera

When: 10-12 Jul 2017 @ 7/19/17 09:00 - 7/19/17 17:00

Where: טכניון חיפה, הפקולטה להנדסת חשמל, בניין מאייר חדר 815




Day 1: Monday 10 July 2017
     FPGA Seminar:
9:00-9:30 Gathering & Light Breakfast
9:30 opening.
9:35-10:15 Highly innovation & customized solutions with programmable silicon (Ilan Hochman – Intel PSG Regional Sales Manager)
10:15 – 11:15 FPGA overview (Lawrence Landis – Intel PSG WW Universities Program Lead)
11:15-11:30 Break
11:30 –12:00 open CL unified desktop for FPGA (Uri Levy Intel SSG System Architect Intel Haifa)
12:00-12:30 FPGA Acceleration Cards using OpenCL – (Reuven Weintraub, Gidel LTD CEO)
12:30-13:00 University program (Young-Schultz, Tanner Intel PSG Software specialist Intel PSG Toronto; Lawrence Landis – Intel PSG WW                                                        Universities Program Lead)
13:00-14:00 Lunch
    FPGA Workshop #1:
14:00 – 17:00 Workshop 1: Introduction to Quartus and FPGAs Hands On Lab
Day 2: Tuesday, 11 July 2017
FPGA Workshop #2 and Workshop #3:
9:00 – 9:30 Gathering & Light Breakfast
9:30 – 13:00 Workshop 2: Embedded Design using Quartus, the Nios Soft Processor and Qsys System Design Tool
13:00-14:00 Lunch
14:00 – 17:00 Workshop 3: Intel-Altera SoC FPGA devices running Linux

Day 3: Wednesday, 12 July 2017
    FPGA Workshop #4
9:00 – 9:30 Gathering & Light Breakfast
9:30 – 13:00 Workshop 4: Intel-Altera OpenCL Software Developer Kit
13:00-14:00 Lunch
14:00 – 16:00 Workshop 4 (Cont) / buffer


Details of the FPGA overview session:

  • What is an FPGA
  • A brief history of FPGAs
  • Where are FPGAs commonly used
  • Intel FPGA product line-up and future roadmap
  • New markets for FPGAs – Machine learning, Artificial Intelligence,Autonomous Driving
  • NN -Demo – Alex net google net
  • FPGA HLD tools
  • Design flows – schematics based, Verilog/VHDL, I++, OpenCL and design tool related trends
  • Intel PSG’s University Program – Development Boards and training  material, research

Detail description of the workshops:
Workshop 1: Introduction to Quartus and FPGAs Hands On Lab
This 3 hour workshop consists of a lecture and lab explaining how FPGAs
work and the associated design flow using the Intel’s Quartus development tools.
The associated lab will guide the participants through project creation and setup,
followed by writing Verilog code for a series of small electronics projects that are
programmed on to the DE10-Standard FPGA development kit which will be provided
by Intel. This course is ideally suited for developer familiar with Boolean
combinational logic and sequential logic who have written small amounts of code in
software languages such as C, Java or Python.
Workshop 2: Embedded Design using Quartus, the Nios Soft Processor and Qsys
System Design Tool
This 3 hour workshop consists of a lecture and lab explaining how to use
Intel’s Nios II processor, associated Qsys system development tool and Eclipse
Software Build Tool to train the student how to assemble a customized embedded
system using a “soft” Nios II processor built from look-up tables and surrounded by
associated peripherals. The associated lab will guide the participants through all
steps from project setup, hardware development, embedded software development
and downloading the resulting project on the DE10-Standard development kit. This
course is ideally suited for developer familiar with computer architecture and
embedded software development in C.

Workshop 3: Intel SoC FPGA devices running Linux
This 3 hour workshop consists of a lecture and lab showing how Intel SoC
FPGA devices combine an ARM9 CPU with an FPGA allowing the development of
exciting new applications. In this tutorial we will look at designing such applications
using the Cyclone V SoC device. We will learn how to run Linux on the device, and
use the associated development environment to create software programs that
communicate with the FPGA. Starting from the basics of memory-mapped
communications, and writing kernel module drivers, we will work our way up to
designing a hardware-accelerated Linux application that offloads computation to a
custom circuit implemented in the FPGA.
Workshop 4: Intel OpenCL Software Developer Kit
In this 3 hour workshop, we will then learn about the Intel OpenCL SDK for
developing hardware-accelerated applications by writing OpenCL code. OpenCL
allows software-centric designers to accelerate algorithms without deep knowledge
of digital hardware design techniques. OpenCL design flows lend themselves to data
flow and massively parallel processing at typically 20% the power of a GPU. In this
workshop, we will give an overview of the OpenCL language, typical applications
used, and how to implement OpenCL coded algorithms on an SoC FPGA based
development kit. This workshop is ideally suited for developer familiar with
computer architecture and high level software programming languages such as C.
HW requirement for the workshop:
Participants should bring their own laptop computer capable of running Windows
operating system. Memory should be in the range of 6-8 GB of physical RAM. The
development tools occupy up to 14GB of disk space depending on which workshop.
The lab training room should include power receptacles for the DE10-
Standard development kits which will be provided by Intel.

Installation guidelines:
The Intel Programmable Solutions Group will be offering 4 workshops on July 10-12th that
require installation of several software tools: Quartus, Putty and VNC. Instructions are for
Windows machines. MAC users should use a Windows Virtual Machine.
Workshops 1 and 2 require Quartus. Workshops 3 and 4 require Putty and VNC. The
published hard drive and memory specs for this technology are 14 GB of hard drive and 6-8
GB of memory, although for these labs will likely require less memory.
1. Quartus Prime Lite Software Installation
Quartus Prime is Altera’s design tool suite. It serves a number of functions:
1. Design creation through the use of HDL languages or schematics
2. System creation and IP integration through the Qsys graphical interface
3. Generation and editing of constraints: timing, pin locations, physical location on die, IO
voltage levels
4. Synthesis of high level language into an FPGA netlist (“mapping” in FPGA terminology)
5. FPGA place and route (“fitting” in FPGA terminology)
6. Generation of a design image (used to program FPGA, “assembly” in FPGA terminology)
7. Timing Analysis
8. Programming/download of design image into FPGA hardware
9. Debugging by insertion of debug logic (in-chip logic analyzer)
10. Interfaces to 3rd party tools such as simulators
11. Launching of Software Build Tools (Eclipse) for Nios II
To download Quartus Prime Lite, follow these instructions:
1. Visit this site:
2. Select version 17.0 and Windows.
3. For the smallest installation and quickest download time, enter only the entries shown
below. No license is required.
4. When prompted, enter your MyAltera account login or create one. Some browsers can be
troublesome during the download process – if you encounter problems, use Microsoft
Internet Explorer. Allow about an hour for installation as the files are fairly large.
One of the steps that happens automatically is installation of the USB Blaster driver
software. Should the USB Blaster software fail to install properly, we can help you install
during the workshop. This only takes a few minutes.

2. PuTTY Installation
PuTTY is a free and open-source terminal emulator, serial console and network file
transfer application. It supports several network protocols, including SCP, SSH, Telnet,
rlogin, and raw socket connection. It can also connect to a serial port.
Go to
Select the .MSI file (32 or 64 bit depending on windows host) and follow install
3. VNCViewer Installation:
VNC works on a client/server model: A VNC viewer (or client) is installed on the local
computer and connects to the server component, which must be installed on the
remote computer. The server transmits a duplicate of the remote computer’s display
screen to the viewer.
Go to
In the drop down box select either EXE x64 or ECE x86 based on your host computer
Click download VNC Viewer.
4. FT232R UART USB Driver Installation
This driver is a USB to serial UARTY driver that allows the computer to talk to the DE10-
Standard board via the UART to USB port.
Go to
Click on VCP Drivers in the “Product Information” section.
Choose the appropriate driver for your OS. There is an executable that you can run to
install (see link in comments section).