Hardware DLL

PGA technology provides the flexibility of on-site programming and re-programming
without going through re-fabrication with a modified design. Partial Reconfiguration (PR)
takes this flexibility one step further, allo
wing the modification of an operating FPGA
design by loading a partial configuration file, usually a partial BIT file. After a full BIT file
configures the FPGA, partial BIT files can be
downloaded to modify reconfigurable regions
in the FPGA without compromising the integr
ity of the applications running on those
parts of the device that are not being reconfigured.

Hardware DLL


Normally, re configuring an FPGA requires it to be held in reset while an external controller reloads a design onto it. Partial reconfiguration allows for critical parts of the design to continue operating while a controller either on the FPGA or off of it loads a partial design into a re-configurable module.

Module-based partial reconfiguration permits to reconfigure distinct modular parts of the design. To ensure the communication across the re-configurable module boundaries, special bus macros ought to be prepared. It works as a fixed routing bridge that connects the re-configurable module with the rest part of the design. Module-based partial reconfiguration requires to perform a set of specific guidelines during at the stage of design specification. Finally for each re-configurable module of the design, separate bit-stream is created. Such a bit-stream is used to perform the partial reconfiguration of an FPGA.

A previous project has demonstrated this capability by swapping different filter modules on the fly, from a single predefined re-configurable area .

The next step is expending this capability , and support a dynamic  re-configurable grid , where a number of different modules in different sizes can be loaded / off loaded as needed.