real time video processing detecting and classifying objects in live sport videos
Projects
Description.
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Many tasks around the house that seems really simple for us sometimes become a big issue for disabled people. By using technology engineers try to help those people to manage and complete some of those tasks in an easier way, so they can be more independent, and live care free. -
in Flash ,Block Erase operations are costly both in execution time as well as in the chips durability (~10,000 erase cycles and chip will malfunction). using Write Only Memory Coding we can reduce the need for Erase operations , extending the chips durability by sacrificing space. -
Bringing a Flash Chip to life. in this project we will connect wires from the flash chip to controller's IO pins and implement the following operations on the controller software: - PageRead - PageWrite - BlockEraseCategories: Flash -
In this project, we present our implementation of a network, consisting solely of mobile devices, that enables performing parallel computing tasks. The code may be installed on Android devices and then implemented algorithms can be run in parallel using the connected devices.Categories: Algorithms -
Merging two sorted arrays is a prominent building block for sorting and other functions. Its ecient parallelization requires balancing the load among compute cores, minimizing the extra work brought about by parallelization, and minimizing inter-thread synchronization requirements. Ecient use of memory is also important. -
PGA technology provides the flexibility of on-site programming and re-programming without going through re-fabrication with a modified design. Partial Reconfiguration (PR) takes this flexibility one step further, allo wing the modification of an operating FPGA design by loading a partial configuration file, usually a partial BIT file. After a full BIT file configures the FPGA, partial BIT files can be downloaded to modify reconfigurable regions in the FPGA without compromising...Categories: FPGA -
PGA technology provides the flexibility of on-site programming and re-programming without going through re-fabrication with a modified design. Partial Reconfiguration (PR) takes this flexibility one step further, allo wing the modification of an operating FPGA design by loading a partial configuration file, usually a partial BIT file. After a full BIT file configures the FPGA, partial BIT files can be downloaded to modify reconfigurable regions in the FPGA without compromising... -
These regions are called Voronoi cells. The Voronoi diagram of a set of points is dual to its Delaunay triangulation. It is named after Georgy Voronoi, and is also called a Voronoi tessellation, a Voronoi decomposition, a Voronoi partition, or a Dirichlet tessellation (after Peter Gustav Lejeune Dirichlet). -
Project description: the Epiphany cores has limited amount of memory , a total of 32kb per core (512kb total) , however , it does have access to 1gb DDR , and SDCARD. in order to overcome the memory limitation , this project will implement a virtual memory interface on the Parallella , allowing for larger programs to run on it. -
neural networks differ from each other by the number of neurons in each layer , number of layers , and inter-connectivity among them. on a given neural network model , the learning process sets each neuron behavior via a small number of parameters. while the learning process is a very demanding computation iteration, the classification itself has a low latency in this project: we will implement a scheduling method ,...